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31.
Altet J. Claeys W. Dilhaire S. Rubio A. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2006,94(8):1519-1533
Measuring techniques of the die surface temperature in integrated circuits are reported as very appropriate for failure analysis, for thermal characterization, and for testing modern devices. The paper is arranged as a survey of techniques oriented towards measuring the temperature dynamics of the circuit surface and presenting and discussing both the merits and drawbacks of each technique with regard to the accuracy, reliability and efficiency of the measurements. Two methods are presented in detail: laser probing methods, based on interferometry and thermoreflectance, and embedded CMOS circuit sensors. For these techniques, the physical principles, the state of the art in figures of merit and some application examples are presented. 相似文献
32.
VM Conraads PG Jorens DG Ebo MJ Claeys JM Bosmans CJ Vrints 《Canadian Metallurgical Quarterly》1998,113(5):1417-1419
We report a patient in whom presumed vasospasm of an angiographically normal coronary artery led to severe transmural myocardial ischemia. To our knowledge, this is the first case in which an allergic reaction to locally applied chlorhexidine caused such a severe reaction. 相似文献
33.
Lukyanchikova N. Petrichuk M. Garbar N. Simoen E. Claeys C. 《Electron Devices, IEEE Transactions on》1996,43(3):417-423
This paper reports on a detailed study of generation-recombination (GR) noise in buried-channel silicon-on-insulator (SOI) pMOSFETs, occurring in the linear operation mode. In particular, the plateau amplitude and the corner frequency (relaxation time τ) of the Lorentzian are investigated as a function of the front (VGf) and of the back gate bias (VGb). It is shown that different cases can be distinguished, depending of the conduction mode of the device, i.e. for surface or buried channel operation. For surface channel operation the GR noise parameters are strongly influenced by the back gate bias and only weakly dependent on VGf. The opposite is true when the front interface starts to deplete, thereby pushing the channel deeper into the Si film. As is shown, the relaxation time depends exponentially on either VGf or VGb. A similar exponential gate-bias dependence is found for the Lorentzian amplitude. Based on the observations, it is concluded that the GR noise originates from the front or the back interface, depending on the operation mode. The effective density of front and back interface traps can be derived from the GR noise amplitude 相似文献
34.
K. Nassim L. Joannes A. CornetS. Dilhaire E. Schaub W. Claeys 《Microelectronics Reliability》1998,38(6-8)
We present an original imaging method to measure the three components of the surface displacement of working power devices with a nanometric resolution. The method takes advantage of the speckle structure of the analysed object recorded on a CCD camera. This method is complementary of IR thermography and provides interesting information concerning stress and reliability in power devices. 相似文献
35.
36.
In this paper, the application of standard capacitance DLTS to high-resistivity (HR) silicon is investigated both theoretically
and experimentally. As will be demonstrated, typical artefacts occur, which are related to the low doping density of the material
(order of a few times 1011 to 1012 cm-3). The high series resistance of a HR-Si diode gives rise to the so-called Q-effect, yielding a reduction of the DLTS peak
amplitude, which is particularly pronounced at room temperature and for p-type material. A second effect is the occurrence
of non-negligible re-emission during the filling pulse, which causes the Arrhenius plot to deviate from a straight line and
is particularly important for repulsive trapping centres. Methods will be discussed to reduce or correct for these phenomena.
They will be illustrated by the practical example of the interstitial Fe donor-level in p-type HR-Si. 相似文献
37.
The empirical relationship between the device transconductance and the input-referred noise spectral density observed on partially depleted SOI n-MOSFETs is examined for other types of devices. As is shown, buried-channel p-MOSFETs processed in the same 1 /spl mu/m CMOS SOI technology show the same behavior. The exponential dependence is also observed for SDI n-MOSFETs fabricated in a 3 /spl mu/m CMOS technology, strongly emphasizing the generality of the result. Furthermore, it is valid both in linear operation (weak and strong inversion) and in saturation. The physical back-ground of this correlation is further elaborated and a new relationship is derived for the noise in the subthreshold regime.<> 相似文献
38.
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40.
Gonzalez M.B. Simoen E. Vissouvanadin B. Verheyen P. Loo R. Claeys C. 《Electron Devices, IEEE Transactions on》2009,56(7):1418-1423
The purpose of this paper is to evaluate the impact of process-induced stress on the generation current of fully strained Si1- xGex source/drain junctions. The Ge content of the compressively strained SiGe epitaxial layer plays a key role in the tensile stress levels present in the underlying Si substrate. Current-voltage (I-V) measurements were employed to further investigate the leakage current enhancement due to the stress-induced bandgap narrowing in the Si depletion region, when no extended defects are formed. An empirical approach is proposed to describe the Ge content dependence of the bandgap-shrinkage-induced leakage current. An increase of the intrinsic carrier concentration as a function of the stress mismatch is observed. Moreover, the role of the epilayer thickness in the generation current is also discussed. 相似文献